Digitech RDS 7.6

You’re about to download the schematics for Digitech RDS 7.6, RDS 1900, RDS 3.6, RDS 2001 digital delay effect processors (ca. 1987).  Its just one document because all four models share a common PCB, with the RDS 7.6 as the most desirable flagship unit.  The lesser models are potentially upgradeable as they share the same PCB and chassis, differing only in RAM chip type, a couple standard logic chips, jumper configuration, and chassis hole pattern.   These are 8-bit effects with NE570 compressor/expander chip to enhance dynamic range.  The Lexicon PCM-42 is a similarly featured unit but with a sweeter sound because of its 12-bit resolution (if I remember correctly) and a more sophisticated analog section, so it commands a much higher price.

 Digitech RDS 123 REV E schematic

Digitech RDS Owners Manual

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Theory of Operation

No warranty that any of this is correct…

Relationship of master clock to sample rate.  Digitech RDS allows manual control over length of the delay by varying the sample rate of a constant-sized RAM buffer.  It has roughly a 3-octave range.  To achieve this, the maximum sample rate is about 8x the minimum.  The master clock is generated with an interesting high-frequency VCO built from 2 opamps (U47 & U48), an NPN transitor, and a 74HC00 CMOS quad NAND gate (U41).  I find that its temperature stability is very poor though.  After a cold start, the delay time constantly decreases for about half an hour.  Its really noticeable if you are sampling a sound and comparing its pitch to the original.  The pitch will keep climbing upward steadily until the unit warms up fully.  I would guess this is due to temperature effects in current-source transistor Q1.  A nice mod would be to temperature-compensate the clock.

Master clock VCO. CV input goes to R121 (right side)

If you are familiar with the CD4069 CMOS VCO project you should see some similarities.  I measured the frequency range of the VCO in an RDS 7.6 with an accurate frequency counter, while varying the front panel delay time control from minimum to maximum.  Of course, the exact values aren’t important because there is an internal trimmer that sets the overall range of delay times.  At its lowest sample rate, the sound is lo-fi but longer delay times are possible than advertised.

296kHz < master clock VCO < 2.35 MHz

Why are these frequencies so high?  It has to do with the inner workings of the analog-to-digital converter (ADC).  This is a successive approximation ADC made with the AM2502PC successive approximation register (U17), an 8-bit current switch DAC (U15), and an LM311 voltage comparator (U12):

Analog input is from a sample-and-hold circuit made with a CD4066 analog switch (U14), a 470pF capacitor (C45), and a JFET opamp (U13A).  The master clock VCO output is applied to pin 9 of the AM2502, and its conversion complete output (pin 2, /CC) goes low 9 clock cycles later.  This is an important fact, because /CC is used as the sample rate clock, after being re-synchronized to the master clock with a 74HC74 D-type flip-flop (U35).  Thus the sample rate of the digital delay is 1/9th the frequency of the master clock.

32.9kHz  < sample rate < 261.1kHz

This reflects the manufacturers claim of 15kHz bandwidth, because bandwidth is limited to half the sample rate as described by the Nyquist-Shannon sampling theorem.  So even at the longest delay time setting, Digitech gives us a generous 15kHz bandwidth.  Although, as the delay time is shortened by increasing the sample rate, bandwidth doesn’t climb to the theoretical max of 130kHz because the unit has a fixed-frequency antialiasing filter (built around op amp U4B) on the input side, and another fixed-frequency lowpass filter on the output (U2B, U1B).

The delay time is directly proportional to the sample rate.  In the owner’s manual we see that 262144 bytes of RAM are used when the unit is in Echo mode.  At 32.9kHz, the delay time is 262144 / 32900 = 7.96 seconds.  At the other end of the delay time dial, the sample rate is 261.1 kHz.  262144 / 261100 = 1.004 seconds.

Okay, so thats how the sample rate, master clock, and delay time are related.  How is the CV generated to control the master clock VCO?  The unit has a built in LFO with Speed and Width controls.  This LFO is built with half of a LM324 quad op-amp (U40).

The delay time knob on the front of the unit is set up as a voltage divider with +5V at the top and 0V at the bottom, so its output is a steady bias between 0 and 5V.   Plugging in to the unit’s rear VCO Control jack interrupts the signal from this potentiometer.  (Some people would rather have these signals mixed together?) The Width control is set up as a voltage divider that ‘crossfades’ between the LFO and VCO Control signal.  When width is at its minimum setting, its output is a steady CV that tells the VCO to oscillate at a constant frequency, i.e. no modulation (provided you aren’t doing something with the rear panel CV input).