CPLD Hello World

After a few days of studying and helpful replies from Steve in tech support, I’d figured out Lattice Semiconductor’s free design software ispLEVER Classic, and successfully downloaded a simple ‘hello world’ demo to a Complex Programmable Logic Device (CPLD) chip. My highest hopes were confirmed… all the steps are possible without writing a line of code. Hooray! You can draw a schematic on the screen and transform it to a piece of hardware in seconds. What a futuristic feeling. The chip itself is some kind of silicon fabric made of zillions of nano-size zombies that reconfigure themselves on command…?! anyway, I’m not scared.  Indeed I’m thrilled with the power of this technique.

The software is free, its called ispLEVER Classic 1.4. Installing it on my Vista laptop wasn’t quite a snap because there are three or four modules to install in order, and you need to find your computer’s MAC address to activate the license. I have to use ‘run as administrator’ to launch it too, but whatever.

The programmer is called ispDOWNLOAD, and it was about $175.

The CPLD chip is ispLSI2032VE, actually nearly obsolete now but the software still supports it.

I think soon I will try to understand Lattice’s MachXO series. They’re related to FPGAs, have built in dual-port RAM, clock generator, clock multiplier… a nice toolbox.

Its inspiring to think that even if the schematic in your head is extra complex, you can just draw it and *boom* little elves build it for you in seconds.

Of course its limited to digital circuits. Not analog yet…

Closeup of the breadboard adapter.  In addition to the socketed CPLD, it has a JTAG 2×5 programming header, a 3.3V regulator, three capacitors, and a resistor.

Note on clock rise times:  CPLDs are capable of running very fast clock rates, 100MHz+.  In my example circuit shown above, I found the counter was behaving anomalously, skipping states.  The root of the problem is related to rise time of the clock pulses.   Logic can be 0 or 1, but the rise time is how long it takes for a transition to occur.  Imagine a horse race and everybody is on the starting line ready to go… the flag goes up, but very slowly.   Will everybody start at exactly the same moment?  This is an analogy for clocking the CPLD.  I found that clock sources that worked fine with 74HC TTL and CD4000 CMOS often do not have a quick enough rise time to clock this CPLD without glitching.  The clock generator built in to my old-school Knight breadboard has a 150 nanosecond rise time, which is too slow.  Experimenting, I found that 10 nanoseconds appears to be fast enough for reliable clocking.  A 74HC244 buffer IC works well for conditioning real-world inputs.